In order to fill the market's steadily growing demand for higher processing capacity, computer and peripheral unit manufacturers are striving to provide faster access to the data stored in memories of both the volatile and nonvolatile types. In addition, there exists a need for lower supply voltages in order to reduce power consumption, while the development of memory cells of the multi-level type commands enhanced discriminating capabilities and more accurate reading.
Thus, a pressing problem is to provide circuitry that can give access to stored information in less time and require less power to do so, while ensuring highly reliable reading of the stored data, to thereby fill the market's demands.
The problem of high-speed reading or sensing has been tackled in several ways. Reading by reference cells involves the use of a nonvolatile memory cell identical with the memory cell being selected by decode blocks; regardless of whether the selected cell is written or not (i.e., has a high or low threshold), the reference cell is always erased (low threshold). In this way, the read circuit is comparing a low threshold cell (thereby drawing a nominal current typical of the physical characteristics of the cell) with a cell whose threshold may be high or low according to how it has been programmed. The selected cell will draw substantially the same current as the reference cell if the threshold is low and no current if the threshold is high.
A read circuit should supply the data output stages with either a high or a low logic value according to whether the threshold of the selected cell is the same as or other than that of the reference cell.
A generic reading arrangement based on the use of a reference cell is shown in FIG. 1. Its principle is that of having a generic selected cell (which may have a high or a low threshold) compared with a constantly virgin cell which, as such, will always be drawing the nominal current that characterizes it.
The reason why reading is performed by comparing a selected cell with a reference cell is that it provides an always virgin cell capable of accommodating the process variations of the array cells throughout the integrated circuit fabrication.
Reading by the reference cell technique actually is not effected by comparing any selected cell with one reference cell but rather by relating the bit line that contains the cell to be read to the reference bit line. Thus, decoding will result in two cells being selected in the same row of the array, namely, the cell to be read and the reference cell. Although the comparison is made with only one reference cell, the term reference bit line is more appropriate.
The reference bit line does solve the problems caused by process variations. The reference bit line approach, in fact, lowers the rate of variations from processing tolerances in the physical and electrical parameters between cells as brought about by the memory array being spread over a fairly large surface. Once the row (word line) is selected, the reference bit line cell and the selected memory cell are allocated to the same axis.
The advantage of the reference cell reading method over the differential cell reading method (wherein data is stored into two memory cells in its straight and negated forms) resides in its reduced silicon area requirements.
As mentioned above, connected to the bit lines are, especially in high storage capacity (4 Mbit, 16 Mbit) devices, the drains of several thousands of memory cells. The capacitances of the junctions associated with the drains of such cells add together into an overall capacitive load of several picofarads. Again, the high bit line capacity is bound to restrict the sensing speed of any reading scheme based on the amplification of a voltage signal developed at the drain of the selected cell (voltage mode operation).
Therefore, current sensing appears preferable. The data discriminating circuitry (sense amplifier) should have a low input impedance and be responsive to current, rather than voltage, signals. The advantage of this method resides basically in its low input impedance allowing the cell current to be injected into the sense amplifier without the bit line voltage undergoing any significant change. In other words, the current method enables the bit line capacitance to be allocated to a node which bears little or no influence on the stored data sensing speed. Usually, before the reading step itself, a "pre-charging" step is also carried out in order to attain optimum voltage at the bit line node for performing the reading.
Reading a cell which has the same threshold voltage as the reference cell includes a privileged reading and a difficult reading. Where the selected cell has a high threshold voltage (and, therefore, no current flowing therethrough), the comparison with the reference cell is easily carried out. With two cells having low thresholds, on the other hand, the comparison becomes more difficult; the current flowing through the two cells is the same, and the sensing circuitry is to detect this condition.
From the literature, many circuits for reading memory cells which are based on the reference cell method are known, and their possible use is tied to the supply voltage whose value tends, as mentioned above, to decrease in today's applications.
What is needed is a novel read circuit for semiconductor memory cells which is based on the reference cell method and includes the best features of conventional circuits but exhibits improved accuracy in discriminating data contained in a cell, while being specifically suitable for use in multi-level cell storage devices.